In the design of a Random Access Memory, it is common practice to array a large number of memory cells in a matrix of rows and columns. Data is typically transferred to and from the memory cells of the same column by means of a pair of electrical conductors, often referred to as the column busses or bit lines. A specific cell among all of those connected between said pair of bit lines is selected by a signal applied to a row address, or word line, which enables all of the memory cells in a row.
The memory cells may be either of the static random access memory type (SRAMs) or of the dynamic random access memory type (DRAMs). In systems using SRAMs, data are usually stored in cross coupled transistor latches where one or more paths to ground can be selectively switched on or off. In DRAMs, data are stored in capacitors by the operation of one or more transistors. In accessing or reading the static type cells, it has heretofore been necessary to permit one of the bit lines to be discharged substantially to ground by currents passing through the memory cells in order to detect a logic "1" (or "0") stored in the cell. Because of the high capacitance of the bit line, this has resulted in a relatively long time period before the bit line is discharged sufficiently for valid data to be read from the cell. In systems using DRAMs, where cells require destructive read cycles, data is read from the memory cell by detecting a voltage pulse on the column bus as the capacitor of the memory cell is either charged or discharged when addressed. Because of the relatively small capacitance of the cells compared to the capacitance of the bit line, the voltage swing is usually small. Detecting the small voltage swing represents a serious problem in designing a sense amplifier circuit which functions reliably.
Generally speaking, as far as Random Access memories are concerned, whichever its type, the output or sensing of information on the bit lines is difficult because of the lack of a full swing logic level. On the other hand, short access times to stored data are particularly difficult to achieve in large scale MOSFET integrated circuits because of the capacitance of various nodes of the memory cells resulting from the manufacturing process.
There have been numerous patents which employ different techniques for providing a full logic output from the data received from the bit lines. For example, see U.S. Pat. No. 3,600,609 issued on Aug. 17, 1971 to Christensen wherein a pair of cross coupled IGFET devices are connected in a race mode and combined with IGFET inverters to convert the differential double rail output of an IGFET memory into a full logic level double rail data output. However, in the Christensen's reference, the "read" amplifier still tends to load the bit lines and does not isolate the bit lines when performing an output function. Additionally, it requires an additional stage of amplification to obtain a full logic output with appropriate levels.
According to U.S. Pat. No. 3,879,621 to J. R. Cavaliere and assigned to the assignee of the present invention, there is described a single stage FET sense amplifier for converting a double rail differential memory output signal into a full logic output signal. The amplifier comprises first and second pairs of FETs coupled together to a pair of common nodes, to form a standard latch. A fifth FET of a second type of conductivity connected to one of the pairs of FETs, is used as an enable device, controlled by a control clock signal. In a preferred embodiment, first and second FETs of the same conductivity type are connected to respective ones of the nodes to act as bit switches to provide good isolation between the bit lines and the latch. The first, second and third FETs are interconnected so that when the first and second transistors conduct, the third transistor is cut off, and vice versa.
So implemented, the disclosed sense amplifier is therefore capable of providing a full logic level output while isolating the bit lines of the memory during sensing. It is a good example of a modern high performance clocked sense amplifier well adapted to CMOS technology.
FIG. 1 of the present application describes the organization of a portion of a CMOS Static Random Access Memory circuit bearing reference 1, which utilizes such a single stage clocked sense amplifier provided with isolation means, to illustrate a typical example of the prior art known to the applicant.
The clocked sense amplifier 2 comprises first and second pairs 3 and 4 of cross coupled transistors. The first pair 3 includes two PFETs T1 and T2, and the second pair 4 includes two NFETs T3 and T4.
The source regions of transistors T1 and T2 are connected to the high voltage of a first power supply (VH) and source regions of transistors T3 and T4 are connected to the low voltage of a second power supply (GND), through an enabling device consisting of a NFET referenced T5, on the gate of which is applied a control clock signal SSA. The five devices T1 and T5 form a clocked latch indicated generally at 5.
Negligible impedance means interconnect the pairs of FETs. In the illustrated instance, the drains of T1 and T3, and the drains of T2 and T4 form nodes 6 and 7 respectively, where the output signal from a selected one of the nodes is available for amplification by the sense amplifier. These nodes 6 and 7 are connected to the inputs of an output latch or a buffer 8, the output of which is applied to an output driver 9. Nodes 6 and 7 are at the same potential as the data lines referenced DLT (Data Line True) and DLC (Data Line Complement), and will often be referred to as data out nodes, because the data is available there. Wires connecting said nodes to the output latch 8 are very short. The data out signal or data DO to be subsequently used for further processing is available on data out terminal 10.
Sense amplifier 2 also comprises means to isolate the clocked latch 5 and its related nodes 6 and 7, from the left or true bit line BLT and the right or complement bit line BLC, to permit said nodes to rise to full signal levels (full logic outputs), while not being loaded by bit lines. Said means consists of so called bit switches. NFETs T6 and T7 are used to that end, i.e., as bit switches to isolate nodes 6 and 7 from the bit lines BLT and BLC respectively, where desired. A control signal BS is applied on the gate electrodes of transistors T6 and T7.
A plurality of four transistor memory cells referenced CA to CN are connected to the bit lines BLT and BLC through two NFETs mounted in a transmission or transfer gate configuration and respectively referenced T8A to T8N and T9A to T9N to form an array 11. The gate electrodes of these FETs, e.g. T8A and T9A for cell CA, are connected to the corresponding word line, e.g. WLA, for READ and WRITE operations. Bit lines BLT and BLC are used as the input (WRITE) or output (READ) path for data movement in and out of the array portion.
Bit lines BLT and BLC are very capacitive due to the summation of all diffusions of transfer devices (T8A to T8N and T9A to T9N) and because long metal wires physically form these bit lines. Resulting capacitances of a column are illustrated in FIG. 1 by capacitors C1 and C2 respectively for BLT and BLC.
The stray capacitances of nodes 6 and 7 are represented by capacitors C3 and C4 and are kept as small as practical. Capacitances of the bit lines BLT and BLC, represented by capacitors C1 and C2 respectively, are inherently large when compared to capacitors C3 and C4.
Optionally, it should be recognized that additional memory cells, which are connected to other pairs of bit lines, may be also coupled to nodes 6 and 7 of the sense amplifier 2 through bus 13, so that one sense amplifier services more than one cell column. The amount F of additional columns may vary from 0 to a number P which depends on the technology used, the memory size and its organization. To date, up to P=15 bit line pairs may be connected to the represented bit line pair consisting of BLT and BLC. In other words a single sense amplifier such as represented in FIG. 1 may service up to 16 memory cell columns. This number P which represents the dotting capabilities of the circuit is limited by the speed of the sense amplifier, which is necessarily a low gain amplifier in the implementation o of FIG. 1. Of course, a separate clock control signal must be employed to permit appropriate gating into the nodes. Bit switches T6 and T7 are also used in cooperating to that purpose.
Finally, the memory circuit 1 also includes a restore circuit 12 for pulling up the potential of bit lines BLT and BLC to the reference voltage VREF=VH-VT (VT being the threshold voltage of an NFET in a reference voltage generator not shown in FIG. 1). A suitable reference voltage generator is detailed in U.S. Pat. No. 4,914,634 (Improved Reference Voltage Generator for CMOS Memories, by C. Akrout, P. Coppens, B. Denis, and P. Urena) and assigned to the same assignee as of the present invention. Circuit 12 comprises three PFETs, T10, T11, and T12, gated by the bit line restore signal BLR. T10 and T11 are coupling transistors with the voltage reference generator. T12 equalizes the charge of capacitors C1 and C2 and therefore the potential of the bit lines. However, it is important to note that nodes 6 and 7 of latch 5 are not equalized. As a result, potentials of said nodes may have opposite binary values compared to the cell content to be accessed when a READ operation is initiated, therefore slowing it down.
The READ operation is as follows. Both bit lines BLT and BLC are charged to VREF. The particular cell is selected by raising the desired word line control signal WL to VH. The selected word line is maintained at this potential a sufficient time to discharge one of the bit lines by a predetermined amount. The clocked latch 5 is set, by bringing up the control clock signal SSA to VH, permitting a full swing logic output to be transmitted to the output latch 8. Clocked latch 5 has to be of the high gain type to ensure proper setting.
During such a READ operation, the sense amplifier 2 amplifies the differential voltage developed first between the bit lines BLT and BLC, and then between the data lines DLT and DLC. This memory organization is limited in speed as it requires the development of a large differential voltage between the sense amplifier internal nodes 6 and 7, i.e. between the two data lines. Moreover, because a full swing operation is needed in the sense amplifier 2, in order to supply the read data into the output latch 8, the access time is increased. In addition, the potentials of nodes 6 and 7 are not equalized, and may correspond to binary values opposite to the data being sensed on the bit lines when a memory cell is accessed. As a result, the setting of the clocked latch 5 has to be done later in order to be sure that the data has been correctly settled on the data lines. Finally, this READ operation is very power consuming when those nodes become highly capacitive with the growth of the memory size.